/**
  ******************************************************************************
  * @file    py32f420_hal_rcc.h
  * @author  MCU Application Team
  * @brief   Header file of RCC HAL module.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2023 Puya Semiconductor Co.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by Puya under BSD 3-Clause license,
  * the "License"; You may not use this file except in compliance with the
  * License. You may obtain a copy of the License at:
  *                        opensource.org/licenses/BSD-3-Clause
  *
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under BSD 3-Clause license,
  * the "License"; You may not use this file except in compliance with the
  * License. You may obtain a copy of the License at:
  *                        opensource.org/licenses/BSD-3-Clause
  *
  ******************************************************************************
  */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __PY32F420_HAL_RCC_H
#define __PY32F420_HAL_RCC_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "py32f420_hal_def.h"


/** @addtogroup PY32F420_HAL_Driver
  * @{
  */

/** @addtogroup RCC
  * @{
  */

/* Exported types ------------------------------------------------------------*/

/** @defgroup RCC_Exported_Types RCC Exported Types
  * @{
  */
  
/**
  * @brief  RCC PLL configuration structure definition
  */
typedef struct
{
  uint32_t PLLState;      /*!< PLLState: The new state of the PLL.
                              This parameter can be a value of @ref RCC_PLL_Config */

  uint32_t PLLSource;     /*!< PLLSource: PLL entry clock source.
                              This parameter must be a value of @ref RCC_PLL_Clock_Source */

  uint32_t PLLMUL;        /*!< PLLMUL: Multiplication factor for PLL VCO input clock
                              This parameter must be a value of @ref RCC_PLL_Multiplication_Factor */
} RCC_PLLInitTypeDef;

/**
  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
  */
typedef struct
{
  uint32_t OscillatorType;        /*!< The oscillators to be configured.
                                        This parameter can be a value of @ref RCC_Oscillator_Type */
#if defined(RCC_HSE_SUPPORT) 
  uint32_t HSEState;              /*!< The new state of the HSE.
                                       This parameter can be a value of @ref RCC_HSE_Config */

  uint32_t HSEFreq;               /*!< The frequency range of the HSE.
                                       This parameter can be a value of @ref RCC_HSE_Freq*/
#endif
#if defined(RCC_LSE_SUPPORT)
  uint32_t LSEState;              /*!<  The new state of the LSE.
                                        This parameter can be a value of @ref RCC_LSE_Config */

  uint32_t LSEDriver;             /*!< The driver factor of the LSE.
                                       This parameter can be a value of @ref RCC_LSE_Driver*/
#endif
  uint32_t HSIState;              /*!< The new state of the HSI.
                                       This parameter can be a value of @ref RCC_HSI_Config */
  
  uint32_t HSICalibrationValue;   /*!< The calibration value of the HSI.
                                       This parameter can be a value of @ref RCC_HSI_Calibration */

  uint32_t HSIDiv;                /*!< The division factor of HSI.
                                       This parameter can be a value of @ref RCC_HSI_Div */
  
  uint32_t LSIState;              /*!<  The new state of the LSI.
                                        This parameter can be a value of @ref RCC_LSI_Config */

  RCC_PLLInitTypeDef PLL;         /*!< PLL structure parameters */

} RCC_OscInitTypeDef;

/**
  * @brief  RCC System, AHB and APB busses clock configuration structure definition
  */
typedef struct
{
  uint32_t ClockType;             /*!< The clock to be configured.
                                       This parameter can be a value of @ref RCC_System_Clock_Type */

  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
                                       This parameter can be a value of @ref RCC_System_Clock_Source */

  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
                                       This parameter can be a value of @ref RCC_AHB_Clock_Source */

  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */

  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
} RCC_ClkInitTypeDef;

/**
  * @}
  */

/* Exported constants --------------------------------------------------------*/
/** @defgroup RCC_Exported_Constants RCC Exported Constants
  * @{
  */

/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
  * @{
  */

#define RCC_PLLSOURCE_HSI           0x00000000U                              /*!< HSI clock selected as PLL entry clock source */
#define RCC_PLLSOURCE_HSE           RCC_PLLCFGR1_PLLSRC                      /*!< HSE clock selected as PLL entry clock source */

/**
  * @}
  */

/** @defgroup RCC_PLL_Multiplication_Factor PLL Multiplication Factor
  * @{
  */
#define RCC_PLL_MUL2                    0x00000000U
#define RCC_PLL_MUL3                    RCC_PLLCFGR1_PLLMUL_0
#define RCC_PLL_MUL4                    RCC_PLLCFGR1_PLLMUL_1
#define RCC_PLL_MUL5                    (RCC_PLLCFGR1_PLLMUL_1 | RCC_PLLCFGR1_PLLMUL_0)
#define RCC_PLL_MUL6                    RCC_PLLCFGR1_PLLMUL_2
#define RCC_PLL_MUL7                    (RCC_PLLCFGR1_PLLMUL_2 | RCC_PLLCFGR1_PLLMUL_0)
#define RCC_PLL_MUL8                    (RCC_PLLCFGR1_PLLMUL_2 | RCC_PLLCFGR1_PLLMUL_1)
#define RCC_PLL_MUL9                    (RCC_PLLCFGR1_PLLMUL_2 | RCC_PLLCFGR1_PLLMUL_1 | RCC_PLLCFGR1_PLLMUL_0)
#define RCC_PLL_MUL10                   RCC_PLLCFGR1_PLLMUL_3
#define RCC_PLL_MUL11                   (RCC_PLLCFGR1_PLLMUL_3 | RCC_PLLCFGR1_PLLMUL_0)
#define RCC_PLL_MUL12                   (RCC_PLLCFGR1_PLLMUL_3 | RCC_PLLCFGR1_PLLMUL_1)
#define RCC_PLL_MUL13                   (RCC_PLLCFGR1_PLLMUL_3 | RCC_PLLCFGR1_PLLMUL_1 | RCC_PLLCFGR1_PLLMUL_0)
#define RCC_PLL_MUL14                   (RCC_PLLCFGR1_PLLMUL_3 | RCC_PLLCFGR1_PLLMUL_2)
#define RCC_PLL_MUL15                   (RCC_PLLCFGR1_PLLMUL_3 | RCC_PLLCFGR1_PLLMUL_2 | RCC_PLLCFGR1_PLLMUL_0)
#define RCC_PLL_MUL16                   (RCC_PLLCFGR1_PLLMUL_3 | RCC_PLLCFGR1_PLLMUL_2 | RCC_PLLCFGR1_PLLMUL_1)
/**
  * @}
  */

/** @defgroup RCC_Oscillator_Type Oscillator Type
  * @{
  */
#define RCC_OSCILLATORTYPE_NONE            0x00000000U
#define RCC_OSCILLATORTYPE_HSE             0x00000001U
#define RCC_OSCILLATORTYPE_HSI             0x00000002U
#define RCC_OSCILLATORTYPE_LSE             0x00000004U
#define RCC_OSCILLATORTYPE_LSI             0x00000008U
/**
  * @}
  */

/** @defgroup RCC_HSE_Config HSE Config
  * @{
  */
#define RCC_HSE_OFF                      0x00000000U                                /*!< HSE clock deactivation */
#define RCC_HSE_ON                       RCC_CR_HSEON                               /*!< HSE clock activation */
#define RCC_HSE_BYPASS                   ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
/**
  * @}
  */

/** @defgroup RCC_HSE_Freq HSE Config
  * @{
  */
#define RCC_HSE_4_8MHz                 0x00000000U                                  /*!< HSE low drive capability */
#define RCC_HSE_8_16MHz                RCC_ECSCR_HSE_DRV_0                          /*!< HSE medium drive capability */
#define RCC_HSE_16_24MHz               RCC_ECSCR_HSE_DRV_0                          /*!< HSE hign drive capability */
#define RCC_HSE_24_32MHz               RCC_ECSCR_HSE_DRV_0                          /*!< HSE very high drive capability */
/**
  * @}
  */

/** @defgroup RCC_HSE_STARTUP HSE settling time Config
  * @{
  */
#define RCC_HSE_STARTUP_NONE         (RCC_ECSCR_HSE_RDYSEL_1 | RCC_ECSCR_HSE_RDYSEL_0)
#define RCC_HSE_STARTUP_LOW          RCC_ECSCR_HSE_RDYSEL_0
#define RCC_HSE_STARTUP_MEDIUM       0x00000000U
#define RCC_HSE_STARTUP_HIGH         RCC_ECSCR_HSE_RDYSEL_1
/**
  * @}
  */

/** @defgroup RCC_LSE_Config LSE Config
  * @{
  */
#define RCC_LSE_OFF                      0x00000000U                                     /*!< LSE clock deactivation */
#define RCC_LSE_ON                       RCC_BDCR_LSEON                                  /*!< LSE clock activation */
#define RCC_LSE_BYPASS                   ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))  /*!< External clock source for LSE clock */
/**
  * @}
  */

/** @defgroup RCC_LSE_Driver LSE Config
  * @{
  */
#define RCC_LSEDRIVE_LOW                 0x00000000U                              /*!< LSE low drive capability */
#define RCC_LSEDRIVE_MEDIUM              RCC_BDCR_LSEDRV_0                        /*!< LSE medium drive capability */
#define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV_1                        /*!< LSE high drive capability */
#define RCC_LSEDRIVE_VERY_HIGH           (RCC_BDCR_LSEDRV_1 | RCC_BDCR_LSEDRV_0)  /*!< LSE vrey high drive capability */
/**
  * @}
  */
  
/** @defgroup RCC_LSE_STARTUP LSE settling time Config
  * @{
  */
#define RCC_LSE_STARTUP_NONE         (RCC_BDCR_LSE_RDYSEL_1 | RCC_BDCR_LSE_RDYSEL_0)
#define RCC_LSE_STARTUP_LOW          RCC_BDCR_LSE_RDYSEL_0
#define RCC_LSE_STARTUP_MEDIUM       0x00000000U
#define RCC_LSE_STARTUP_HIGH         RCC_BDCR_LSE_RDYSEL_1
/**
  * @}
  */
  
/** @defgroup RCC_HSI_Config HSI Config
  * @{
  */
#define RCC_HSI_OFF                      0x00000000U                      /*!< HSI clock deactivation */
#define RCC_HSI_ON                       RCC_CR_HSION                     /*!< HSI clock activation */
/**
  * @}
  */
/** @defgroup RCC_HSI_Calibration HSI Calibration
* @{
*/
#define RCC_HSICALIBRATION_8MHz        ((0x0<<16) | ((*(uint32_t *)(0x1FFF1A80)) & 0xFFFF))  /*!< 8MHz HSI calibration trimming value */
#define RCC_HSICALIBRATION_16MHz       ((0x1<<16) | ((*(uint32_t *)(0x1FFF1A84)) & 0xFFFF))  /*!< 16MHz HSI calibration trimming value */
#define RCC_HSICALIBRATION_24MHz       ((0x2<<16) | ((*(uint32_t *)(0x1FFF1A8C)) & 0xFFFF))  /*!< 24MHz HSI calibration trimming value */
#define RCC_HSICALIBRATION_48MHz       ((0x3<<16) | ((*(uint32_t *)(0x1FFF1A90)) & 0xFFFF))  /*!< 48MHz HSI calibration trimming value */
/**
  * @}
  */
  
/** @defgroup RCC_HSI_Div HSI Div
  * @{
  */
#define RCC_HSI_DIV1                   0x00000000U                                        /*!< HSI clock is not divided */
#define RCC_HSI_DIV2                   RCC_CR_HSIDIV_0                                    /*!< HSI clock is divided by 2 */
#define RCC_HSI_DIV4                   RCC_CR_HSIDIV_1                                    /*!< HSI clock is divided by 4 */
#define RCC_HSI_DIV8                   (RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0)                  /*!< HSI clock is divided by 8 */
/**
  * @}
  */

/** @defgroup RCC_LSI_Config LSI Config
  * @{
  */
#define RCC_LSI_OFF                      0x00000000U              /*!< LSI clock deactivation */
#define RCC_LSI_ON                       RCC_BDCR_LSION           /*!< LSI clock activation */
/**
  * @}
  */

/** @defgroup RCC_PLL_Config PLL Config
  * @{
  */
#define RCC_PLL_NONE                      0x00000000U  /*!< PLL is not configured */
#define RCC_PLL_OFF                       0x00000001U  /*!< PLL deactivation */
#define RCC_PLL_ON                        0x00000002U  /*!< PLL activation */
/**
  * @}
  */

/** @defgroup RCC_System_Clock_Type System Clock Type
  * @{
  */
#define RCC_CLOCKTYPE_SYSCLK             0x00000001U /*!< SYSCLK to configure */
#define RCC_CLOCKTYPE_HCLK               0x00000002U /*!< HCLK to configure */
#define RCC_CLOCKTYPE_PCLK1              0x00000004U /*!< PCLK1 to configure */
#define RCC_CLOCKTYPE_PCLK2              0x00000008U /*!< PCLK2 to configure */
/**
  * @}
  */

/** @defgroup RCC_System_Clock_Source System Clock Source
  * @{
  */
#define RCC_SYSCLKSOURCE_HSISYS          RCC_CFGR1_SW_HSISYS /*!< HSISYS selected as system clock */
#define RCC_SYSCLKSOURCE_HSE             RCC_CFGR1_SW_HSE    /*!< HSE selected as system clock */
#define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR1_SW_PLL    /*!< PLL selected as system clock */
/**
  * @}
  */

/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
  * @{
  */
#define RCC_SYSCLKSOURCE_STATUS_HSISYS   RCC_CFGR1_SWS_HSISYS         /*!< HSISYS used as system clock */
#define RCC_SYSCLKSOURCE_STATUS_HSE      RCC_CFGR1_SWS_HSE            /*!< HSE used as system clock */
#define RCC_SYSCLKSOURCE_STATUS_PLLCLK   RCC_CFGR1_SWS_PLL            /*!< PLL used as system clock */
/**
  * @}
  */

/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
  * @{
  */
#define RCC_SYSCLK_DIV1                  0x00000000U   /*!< SYSCLK not divided */
#define RCC_SYSCLK_DIV2                  RCC_CFGR1_HPRE_3   /*!< SYSCLK divided by 2 */
#define RCC_SYSCLK_DIV4                  (RCC_CFGR1_HPRE_3 | RCC_CFGR1_HPRE_0)   /*!< SYSCLK divided by 4 */
#define RCC_SYSCLK_DIV8                  (RCC_CFGR1_HPRE_3 | RCC_CFGR1_HPRE_1)   /*!< SYSCLK divided by 8 */
#define RCC_SYSCLK_DIV16                 (RCC_CFGR1_HPRE_3 | RCC_CFGR1_HPRE_1 | RCC_CFGR1_HPRE_0)  /*!< SYSCLK divided by 16 */
#define RCC_SYSCLK_DIV64                 (RCC_CFGR1_HPRE_3 | RCC_CFGR1_HPRE_2)  /*!< SYSCLK divided by 64 */
#define RCC_SYSCLK_DIV128                (RCC_CFGR1_HPRE_3 | RCC_CFGR1_HPRE_2 | RCC_CFGR1_HPRE_0) /*!< SYSCLK divided by 128 */
#define RCC_SYSCLK_DIV256                (RCC_CFGR1_HPRE_3 | RCC_CFGR1_HPRE_2 | RCC_CFGR1_HPRE_1) /*!< SYSCLK divided by 256 */
#define RCC_SYSCLK_DIV512                (RCC_CFGR1_HPRE_3 | RCC_CFGR1_HPRE_2 | RCC_CFGR1_HPRE_1   | RCC_CFGR1_HPRE_0) /*!< SYSCLK divided by 512 */
/**
  * @}
  */

/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
  * @{
  */
#define RCC_HCLK_DIV1                    0x00000000U                                           /*!< HCLK divided by 1 */
#define RCC_HCLK_DIV2                    RCC_CFGR1_PPRE1_2                                       /*!< HCLK divided by 2 */
#define RCC_HCLK_DIV4                    (RCC_CFGR1_PPRE1_2 | RCC_CFGR1_PPRE1_0)                   /*!< HCLK divided by 4 */
#define RCC_HCLK_DIV8                    (RCC_CFGR1_PPRE1_2 | RCC_CFGR1_PPRE1_1)                   /*!< HCLK divided by 8 */
#define RCC_HCLK_DIV16                   (RCC_CFGR1_PPRE1_2 | RCC_CFGR1_PPRE1_1 | RCC_CFGR1_PPRE1_0) /*!< HCLK divided by 16 */
/**
  * @}
  */

/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
  * @{
  */
#define RCC_RTCCLKSOURCE_NONE            0x00000000U              /*!< No clock */
#if defined(RCC_LSE_SUPPORT)
#define RCC_RTCCLKSOURCE_LSE             RCC_BDCR_RTCSEL_0        /*!< LSE oscillator clock used as RTC clock */
#endif
#define RCC_RTCCLKSOURCE_LSI             RCC_BDCR_RTCSEL_1        /*!< LSI oscillator clock used as RTC clock */
#if defined(RCC_HSE_SUPPORT) 
#define RCC_RTCCLKSOURCE_HSE_DIV32       (RCC_BDCR_RTCSEL_1 | RCC_BDCR_RTCSEL_0)      /*!< HSE oscillator clock divided by 32 used as RTC clock */
#define RCC_RTCCLKSOURCE_HSE_DIV128      (RCC_CCIPR2_RTC_HSEDIV_SEL_0 | RCC_BDCR_RTCSEL_1 | RCC_BDCR_RTCSEL_0)      /*!< HSE oscillator clock divided by 128 used as RTC clock */
#define RCC_RTCCLKSOURCE_HSE_DIV8        (RCC_CCIPR2_RTC_HSEDIV_SEL_1 | RCC_BDCR_RTCSEL_1 | RCC_BDCR_RTCSEL_0)      /*!< HSE oscillator clock divided by 8 used as RTC clock */
#endif
/**
  * @}
  */

/** @defgroup RCC_MCO_Index MCO Index
  * @{
  */
#define RCC_MCO1_PC9                   0x00000001U
#define RCC_MCO1_PC14                  0x00000002U
#define RCC_MCO1_PD1                   0x00000004U
#define RCC_MCO1_PD5                   0x00000008U
#define RCC_MCO2_PA4                   0x00000010U
#define RCC_MCO2_PA8                   0x00000020U
#define RCC_MCO2_PC15                  0x00000040U
#define RCC_MCO2_PD11                  0x00000080U
/**
  * @}
  */

/** @defgroup RCC_MCOx_Clock_Source MCOx Clock Source
  * @{
  */
#define RCC_MCOSOURCE_NOCLOCK         0x00000000U                                /*!< MCO output disabled, no clock on MCO */
#define RCC_MCOSOURCE_SYSCLK          RCC_CFGR1_MCO1SEL_0                        /*!< SYSCLK selection as MCO source */
#define RCC_MCOSOURCE_HSI             RCC_CFGR1_MCO1SEL_1                        /*!< HSI selection as MCO source */
#if defined(RCC_HSE_SUPPORT) 
#define RCC_MCOSOURCE_HSE             (RCC_CFGR1_MCO1SEL_1 | RCC_CFGR1_MCO1SEL_0)  /*!< HSE selection as MCO source */
#endif
#define RCC_MCOSOURCE_PLLCLK          RCC_CFGR1_MCO1SEL_2                          /*!< PLLCLK selection as MCO source */
#define RCC_MCOSOURCE_LSI             (RCC_CFGR1_MCO1SEL_2 | RCC_CFGR1_MCO1SEL_0)  /*!< LSI selection as MCO source */
#if defined(RCC_LSE_SUPPORT)
#define RCC_MCOSOURCE_LSE             (RCC_CFGR1_MCO1SEL_2 | RCC_CFGR1_MCO1SEL_1)  /*!< LSE selection as MCO source */
#endif
#define RCC_MCOSOURCE_HSI10M          (RCC_CFGR1_MCO1SEL_3 | RCC_CFGR1_MCO1SEL_0)
#define RCC_MCOSOURCE_HCLK            (RCC_CFGR1_MCO1SEL_3 | RCC_CFGR1_MCO1SEL_1)
#define RCC_MCOSOURCE_PCLK1           (RCC_CFGR1_MCO1SEL_3 | RCC_CFGR1_MCO1SEL_1 | RCC_CFGR1_MCO1SEL_0)
#define RCC_MCOSOURCE_PCLK2           (RCC_CFGR1_MCO1SEL_3 | RCC_CFGR1_MCO1SEL_2)
/**
  * @}
  */

/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
  * @{
  */
#define RCC_MCODIV_1                   0x00000000U                                                                              /*!< MCO not divided */
#define RCC_MCODIV_2                   (RCC_CFGR1_MCO1PRE_3)                                                                    /*!< MCO divided by 2 */
#define RCC_MCODIV_4                   (RCC_CFGR1_MCO1PRE_3 | RCC_CFGR1_MCO1PRE_0)                                              /*!< MCO divided by 4 */
#define RCC_MCODIV_8                   (RCC_CFGR1_MCO1PRE_3 | RCC_CFGR1_MCO1PRE_1)                                              /*!< MCO divided by 8 */
#define RCC_MCODIV_16                  (RCC_CFGR1_MCO1PRE_3 | RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_0)                        /*!< MCO divided by 16 */
#define RCC_MCODIV_32                  (RCC_CFGR1_MCO1PRE_3 | RCC_CFGR1_MCO1PRE_2)                                              /*!< MCO divided by 32 */
#define RCC_MCODIV_64                  (RCC_CFGR1_MCO1PRE_3 | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_0)                        /*!< MCO divided by 64 */
#define RCC_MCODIV_128                 (RCC_CFGR1_MCO1PRE_3 | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_1)                        /*!< MCO divided by 128 */
#define RCC_MCODIV_256                 (RCC_CFGR1_MCO1PRE_3 | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_0)  /*!< MCO divided by 256 */
/**
  * @}
  */

/** @defgroup RCC_Interrupt Interrupts
  * @{
  */
#define RCC_IT_LSIRDY                    RCC_CIFR_LSIRDYF   /*!< LSI Ready Interrupt flag */
#define RCC_IT_LSERDY                    RCC_CIFR_LSERDYF   /*!< LSE Ready Interrupt flag */
#define RCC_IT_HSIRDY                    RCC_CIFR_HSIRDYF   /*!< HSI Ready Interrupt flag */
#define RCC_IT_HSERDY                    RCC_CIFR_HSERDYF   /*!< HSE Ready Interrupt flag */
#define RCC_IT_PLLRDY                    RCC_CIFR_PLLRDYF   /*!< PLL Ready Interrupt flag */
#define RCC_IT_CSS                       RCC_CIFR_HSECSSF   /*!< Clock Security System Interrupt flag */
/**
  * @}
  */

/** @defgroup RCC_Flag Flags
  *        Elements values convention: XXXYYYYYb
  *           - YYYYY  : Flag position in the register
  *           - XXX  : Register index
  *                 - 001: CR register
  *                 - 010: BDCR register
  *                 - 011: CSR register
  *                 - 100: CFGR1 register
  * @{
  */
/* Flags in the CR register */
#define RCC_FLAG_HSIRDY                  ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */
#define RCC_FLAG_HSERDY                  ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */
#define RCC_FLAG_PLLRDY                  ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */

/* Flags in the CSR register */
#define RCC_FLAG_EPWM_PRST              ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_EPWM_PRST_RELEASE_Pos))    /*!< EPWM APB reset flag */
#define RCC_FLAG_EPWM_SFTRST            ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_EPWM_SFTRST_RELEASE_Pos))  /*!< EPWM software reset flag */
#define RCC_FLAG_PLLULRST                ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PLLULRSTF_Pos))      /*!< PLL unlock reset flag */
#define RCC_FLAG_OBLRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos))        /*!< Option byte loader reset flag */
#define RCC_FLAG_PINRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos))        /*!< PIN reset flag reset flag*/
#define RCC_FLAG_PWRRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PWRRSTF_Pos))        /*!< POR/PDR reset flag */
#define RCC_FLAG_SFTRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos))        /*!< Software Reset flag */
#define RCC_FLAG_IWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos))       /*!< Independent Watchdog reset flag */
#define RCC_FLAG_WWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos))       /*!< Window watchdog reset flag */
#define RCC_FLAG_LPWRRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos))       /*!< Low-Power reset flag */

/* Flags in the BDCR register */
#define RCC_FLAG_LSIRDY                  ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */
#define RCC_FLAG_LSERDY                  ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */
/**
  * @}
  */

/**
  * @}
  */

/* Exported macro ------------------------------------------------------------*/

/** @defgroup RCC_Exported_Macros RCC Exported Macros
  * @{
  */

/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
  * @brief  Enable or disable the AHB1 peripheral clock.
  * @note   After reset, the peripheral clock (used for registers read/write access)
  *         is disabled and the application software has to enable this clock before
  *         using it.
  * @{
  */
#define __HAL_RCC_DMA_CLK_ENABLE()    do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHBENR1, RCC_AHBENR1_DMAEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->AHBENR1, RCC_AHBENR1_DMAEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

#define __HAL_RCC_SRAM_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHBENR1, RCC_AHBENR1_SRAMSMEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->AHBENR1, RCC_AHBENR1_SRAMSMEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

#define __HAL_RCC_CRC_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHBENR1, RCC_AHBENR1_CRCEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->AHBENR1, RCC_AHBENR1_CRCEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

#define __HAL_RCC_DMA_CLK_DISABLE()       (RCC->AHBENR1 &= ~(RCC_AHBENR1_DMAEN))
#define __HAL_RCC_SRAM_CLK_DISABLE()      (RCC->AHBENR1 &= ~(RCC_AHBENR1_SRAMSMEN))
#define __HAL_RCC_CRC_CLK_DISABLE()       (RCC->AHBENR1 &= ~(RCC_AHBENR1_CRCEN))
/**
  * @}
  */

/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
  * @brief  Get the enable or disable status of the AHB peripheral clock.
  * @note   After reset, the peripheral clock (used for registers read/write access)
  *         is disabled and the application software has to enable this clock before
  *         using it.
  * @{
  */
#define __HAL_RCC_DMA_IS_CLK_ENABLED()        ((RCC->AHBENR1 & (RCC_AHBENR1_DMAEN)) != RESET)
#define __HAL_RCC_SRAM_IS_CLK_ENABLED()       ((RCC->AHBENR1 & (RCC_AHBENR1_SRAMSMEN)) != RESET)
#define __HAL_RCC_CRC_IS_CLK_ENABLED()        ((RCC->AHBENR1 & (RCC_AHBENR1_CRCEN)) != RESET)

#define __HAL_RCC_DMA_IS_CLK_DISABLED()       ((RCC->AHBENR1 & (RCC_AHBENR1_DMAEN)) == RESET)
#define __HAL_RCC_SRAM_IS_CLK_DISABLED()      ((RCC->AHBENR1 & (RCC_AHBENR1_SRAMSMEN)) == RESET)
#define __HAL_RCC_CRC_IS_CLK_DISABLED()       ((RCC->AHBENR1 & (RCC_AHBENR1_CRCEN)) == RESET)
/**
  * @}
  */

/** @defgroup RCC_AHB2_Clock_Enable_Disable AHB2 Clock Enable Disable
  * @brief  Enable or disable the IO Ports clock.
  * @note   After reset, the IO ports clock (used for registers read/write access)
  *         is disabled and the application software has to enable this clock before
  *         using it.
  * @{
  */
#define __HAL_RCC_GPIOA_CLK_ENABLE()           do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHBENR2, RCC_AHBENR2_GPIOAEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHBENR2, RCC_AHBENR2_GPIOAEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0U)

#define __HAL_RCC_GPIOB_CLK_ENABLE()           do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHBENR2, RCC_AHBENR2_GPIOBEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHBENR2, RCC_AHBENR2_GPIOBEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0U)

#define __HAL_RCC_GPIOC_CLK_ENABLE()           do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHBENR2, RCC_AHBENR2_GPIOCEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHBENR2, RCC_AHBENR2_GPIOCEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0U)

#define __HAL_RCC_GPIOD_CLK_ENABLE()           do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHBENR2, RCC_AHBENR2_GPIODEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHBENR2, RCC_AHBENR2_GPIODEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0U)

#define __HAL_RCC_GPIOA_CLK_DISABLE()          CLEAR_BIT(RCC->AHBENR2, RCC_AHBENR2_GPIOAEN)
#define __HAL_RCC_GPIOB_CLK_DISABLE()          CLEAR_BIT(RCC->AHBENR2, RCC_AHBENR2_GPIOBEN)
#define __HAL_RCC_GPIOC_CLK_DISABLE()          CLEAR_BIT(RCC->AHBENR2, RCC_AHBENR2_GPIOCEN)
#define __HAL_RCC_GPIOD_CLK_DISABLE()          CLEAR_BIT(RCC->AHBENR2, RCC_AHBENR2_GPIODEN)
/**
  * @}
  */

/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
  * @brief  Check whether the AHB2 peripheral clock is enabled or not.
  * @note   After reset, the peripheral clock (used for registers read/write access)
  *         is disabled and the application software has to enable this clock before
  *         using it.
  * @{
  */
#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()       (READ_BIT(RCC->AHBENR2, RCC_AHBENR2_GPIOAEN) != RESET)
#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()       (READ_BIT(RCC->AHBENR2, RCC_AHBENR2_GPIOBEN) != RESET)
#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()       (READ_BIT(RCC->AHBENR2, RCC_AHBENR2_GPIOCEN) != RESET)
#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()       (READ_BIT(RCC->AHBENR2, RCC_AHBENR2_GPIODEN) != RESET)

#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()      (READ_BIT(RCC->AHBENR2, RCC_AHBENR2_GPIOAEN) == RESET)
#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()      (READ_BIT(RCC->AHBENR2, RCC_AHBENR2_GPIOBEN) == RESET)
#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()      (READ_BIT(RCC->AHBENR2, RCC_AHBENR2_GPIOCEN) == RESET)
#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()      (READ_BIT(RCC->AHBENR2, RCC_AHBENR2_GPIODEN) == RESET)
/**
  * @}
  */

/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
  * @note   After reset, the peripheral clock (used for registers read/write access)
  *         is disabled and the application software has to enable this clock before
  *         using it.
  * @{
  */
#define __HAL_RCC_TIM1_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM1EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)
#define __HAL_RCC_TIM2_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

#define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM8EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM8EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

#define __HAL_RCC_TIM1_CLK_DISABLE()      (RCC->APBENR1 &= ~(RCC_APBENR1_TIM1EN))
#define __HAL_RCC_TIM2_CLK_DISABLE()      (RCC->APBENR1 &= ~(RCC_APBENR1_TIM2EN))
#define __HAL_RCC_TIM3_CLK_DISABLE()      (RCC->APBENR1 &= ~(RCC_APBENR1_TIM3EN))
#define __HAL_RCC_TIM6_CLK_DISABLE()      (RCC->APBENR1 &= ~(RCC_APBENR1_TIM6EN))
#define __HAL_RCC_TIM7_CLK_DISABLE()      (RCC->APBENR1 &= ~(RCC_APBENR1_TIM7EN))
#define __HAL_RCC_TIM8_CLK_DISABLE()      (RCC->APBENR1 &= ~(RCC_APBENR1_TIM8EN))
/**
  * @}
  */

/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
  * @brief  Get the enable or disable status of the APB1 peripheral clock.
  * @note   After reset, the peripheral clock (used for registers read/write access)
  *         is disabled and the application software has to enable this clock before
  *         using it.
  * @{
  */
#define __HAL_RCC_TIM1_IS_CLK_ENABLED()       ((RCC->APBENR1 & (RCC_APBENR1_TIM1EN)) != RESET)
#define __HAL_RCC_TIM2_IS_CLK_ENABLED()       ((RCC->APBENR1 & (RCC_APBENR1_TIM2EN)) != RESET)
#define __HAL_RCC_TIM3_IS_CLK_ENABLED()       ((RCC->APBENR1 & (RCC_APBENR1_TIM3EN)) != RESET)
#define __HAL_RCC_TIM6_IS_CLK_ENABLED()       ((RCC->APBENR1 & (RCC_APBENR1_TIM6EN)) != RESET)
#define __HAL_RCC_TIM7_IS_CLK_ENABLED()       ((RCC->APBENR1 & (RCC_APBENR1_TIM7EN)) != RESET)
#define __HAL_RCC_TIM8_IS_CLK_ENABLED()       ((RCC->APBENR1 & (RCC_APBENR1_TIM8EN)) != RESET)

#define __HAL_RCC_TIM1_IS_CLK_DISABLED()      ((RCC->APBENR1 & (RCC_APBENR1_TIM1EN)) == RESET)
#define __HAL_RCC_TIM2_IS_CLK_DISABLED()      ((RCC->APBENR1 & (RCC_APBENR1_TIM2EN)) == RESET)
#define __HAL_RCC_TIM3_IS_CLK_DISABLED()      ((RCC->APBENR1 & (RCC_APBENR1_TIM3EN)) == RESET)
#define __HAL_RCC_TIM6_IS_CLK_DISABLED()      ((RCC->APBENR1 & (RCC_APBENR1_TIM6EN)) == RESET)
#define __HAL_RCC_TIM7_IS_CLK_DISABLED()      ((RCC->APBENR1 & (RCC_APBENR1_TIM7EN)) == RESET)
#define __HAL_RCC_TIM8_IS_CLK_DISABLED()      ((RCC->APBENR1 & (RCC_APBENR1_TIM8EN)) == RESET)
/**
  * @}
  */
/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
  * @brief  Enable or disable the Low Speed APB (APB2) peripheral clock.
  * @note   After reset, the peripheral clock (used for registers read/write access)
  *         is disabled and the application software has to enable this clock before
  *         using it.
  * @{
  */
#define __HAL_RCC_EPWM_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR2, RCC_APBENR2_EPWMEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_EPWMEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

#define __HAL_RCC_LPTIM_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR2, RCC_APBENR2_LPTIMEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_LPTIMEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

#define __HAL_RCC_WWDG_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR2, RCC_APBENR2_WWDGEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_WWDGEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

#define __HAL_RCC_EPWM_CLK_DISABLE()       (RCC->APBENR2 &= ~(RCC_APBENR2_EPWMEN))
#define __HAL_RCC_LPTIM_CLK_DISABLE()       (RCC->APBENR2 &= ~(RCC_APBENR2_LPTIMEN))
#define __HAL_RCC_WWDG_CLK_DISABLE()        (RCC->APBENR2 &= ~(RCC_APBENR2_WWDGEN))
/**
  * @}
  */
/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
  * @brief  Get the enable or disable status of the APB2 peripheral clock.
  * @note   After reset, the peripheral clock (used for registers read/write access)
  *         is disabled and the application software has to enable this clock before
  *         using it.
  * @{
  */
#define __HAL_RCC_EPWM_IS_CLK_ENABLED()     ((RCC->APBENR2 & (RCC_APBENR2_EPWMEN)) != RESET)
#define __HAL_RCC_LPTIM_IS_CLK_ENABLED()     ((RCC->APBENR2 & (RCC_APBENR2_LPTIMEN)) != RESET)
#define __HAL_RCC_WWDG_IS_CLK_ENABLED()      ((RCC->APBENR2 & (RCC_APBENR2_WWDGEN)) != RESET)

#define __HAL_RCC_EPWM_IS_CLK_DISABLED()    ((RCC->APBENR2 & (RCC_APBENR2_EPWMEN)) == RESET)
#define __HAL_RCC_LPTIM_IS_CLK_DISABLED()    ((RCC->APBENR2 & (RCC_APBENR2_LPTIMEN)) == RESET)
#define __HAL_RCC_WWDG_IS_CLK_DISABLED()     ((RCC->APBENR2 & (RCC_APBENR2_WWDGEN)) == RESET)
/**
  * @}
  */

/** @defgroup RCC_APB3_Clock_Enable_Disable APB3 Clock Enable Disable
  * @brief  Enable or disable the High Speed APB (APB3) peripheral clock.
  * @note   After reset, the peripheral clock (used for registers read/write access)
  *         is disabled and the application software has to enable this clock before
  *         using it.
  * @{
  */
#define __HAL_RCC_UART1_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR3, RCC_APBENR3_UART1EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR4, RCC_APBENR3_UART1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

#define __HAL_RCC_UART2_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR3, RCC_APBENR3_UART2EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR3, RCC_APBENR3_UART2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)
#define __HAL_RCC_USART_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR3, RCC_APBENR3_USARTEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR3, RCC_APBENR3_USARTEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)
#define __HAL_RCC_LPUART_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR3, RCC_APBENR3_LPUARTEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR3, RCC_APBENR3_LPUARTEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)
#define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR3, RCC_APBENR3_I2C1EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR3, RCC_APBENR3_I2C1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)
#define __HAL_RCC_I2C2_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR3, RCC_APBENR3_I2C2EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR3, RCC_APBENR3_I2C2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)
#define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR3, RCC_APBENR3_SPI1EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR3, RCC_APBENR3_SPI1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)
#define __HAL_RCC_SPI2_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR3, RCC_APBENR3_SPI2EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR3, RCC_APBENR3_SPI2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

#define __HAL_RCC_FDCAN_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR3, RCC_APBENR3_FDCANEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR3, RCC_APBENR3_FDCANEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)
#define __HAL_RCC_UART1_CLK_DISABLE()      (RCC->APBENR3 &= ~(RCC_APBENR3_UART1EN))
#define __HAL_RCC_UART2_CLK_DISABLE()      (RCC->APBENR3 &= ~(RCC_APBENR3_UART2EN))
#define __HAL_RCC_USART_CLK_DISABLE()      (RCC->APBENR3 &= ~(RCC_APBENR3_USARTEN))
#define __HAL_RCC_LPUART_CLK_DISABLE()     (RCC->APBENR3 &= ~(RCC_APBENR3_LPUARTEN))
#define __HAL_RCC_I2C1_CLK_DISABLE()       (RCC->APBENR3 &= ~(RCC_APBENR3_I2C1EN))
#define __HAL_RCC_I2C2_CLK_DISABLE()       (RCC->APBENR3 &= ~(RCC_APBENR3_I2C2EN))
#define __HAL_RCC_SPI1_CLK_DISABLE()       (RCC->APBENR3 &= ~(RCC_APBENR3_SPI1EN))
#define __HAL_RCC_SPI2_CLK_DISABLE()       (RCC->APBENR3 &= ~(RCC_APBENR3_SPI2EN))
#define __HAL_RCC_FDCAN_CLK_DISABLE()        (RCC->APBENR3 &= ~(RCC_APBENR3_FDCANEN))
/**
  * @}
  */

/** @defgroup RCC_APB3_Peripheral_Clock_Enable_Disable_Status APB3 Peripheral Clock Enable Disable Status
  * @brief  Get the enable or disable status of the APB3 peripheral clock.
  * @note   After reset, the peripheral clock (used for registers read/write access)
  *         is disabled and the application software has to enable this clock before
  *         using it.
  * @{
  */
#define __HAL_RCC_UART1_IS_CLK_ENABLED()     ((RCC->APBENR3 & (RCC_APBENR3_UART1EN)) != RESET)
#define __HAL_RCC_UART2_IS_CLK_ENABLED()     ((RCC->APBENR3 & (RCC_APBENR3_UART2EN)) != RESET)
#define __HAL_RCC_USART_IS_CLK_ENABLED()     ((RCC->APBENR3 & (RCC_APBENR3_USARTEN)) != RESET)
#define __HAL_RCC_LPUART_IS_CLK_ENABLED()    ((RCC->APBENR3 & (RCC_APBENR3_LPUARTEN)) != RESET)
#define __HAL_RCC_I2C1_IS_CLK_ENABLED()      ((RCC->APBENR3 & (RCC_APBENR3_I2C1EN)) != RESET)
#define __HAL_RCC_I2C2_IS_CLK_ENABLED()      ((RCC->APBENR3 & (RCC_APBENR3_I2C2EN)) != RESET)
#define __HAL_RCC_SPI1_IS_CLK_ENABLED()      ((RCC->APBENR3 & (RCC_APBENR3_SPI1EN)) != RESET)
#define __HAL_RCC_SPI2_IS_CLK_ENABLED()      ((RCC->APBENR3 & (RCC_APBENR3_SPI2EN)) != RESET)
#define __HAL_RCC_FDCAN_IS_CLK_ENABLED()       ((RCC->APBENR3 & (RCC_APBENR3_FDCANEN)) != RESET)

#define __HAL_RCC_UART1_IS_CLK_DISABLED()    ((RCC->APBENR3 & (RCC_APBENR3_UART1EN)) == RESET)
#define __HAL_RCC_UART2_IS_CLK_DISABLED()    ((RCC->APBENR3 & (RCC_APBENR3_UART2EN)) == RESET)
#define __HAL_RCC_USART_IS_CLK_DISABLED()    ((RCC->APBENR3 & (RCC_APBENR3_USARTEN)) == RESET)
#define __HAL_RCC_LPUART_IS_CLK_DISABLED()   ((RCC->APBENR3 & (RCC_APBENR3_LPUARTEN)) == RESET)
#define __HAL_RCC_I2C1_IS_CLK_DISABLED()     ((RCC->APBENR3 & (RCC_APBENR3_I2C1EN)) == RESET)
#define __HAL_RCC_I2C2_IS_CLK_DISABLED()     ((RCC->APBENR3 & (RCC_APBENR3_I2C2EN)) == RESET)
#define __HAL_RCC_SPI1_IS_CLK_DISABLED()     ((RCC->APBENR3 & (RCC_APBENR3_SPI1EN)) == RESET)
#define __HAL_RCC_SPI2_IS_CLK_DISABLED()     ((RCC->APBENR3 & (RCC_APBENR3_SPI2EN)) == RESET)
#define __HAL_RCC_FDCAN_IS_CLK_DISABLED()      ((RCC->APBENR3 & (RCC_APBENR3_FDCANEN)) == RESET)

/**
  * @}
  */

/** @defgroup RCC_APB4_Clock_Enable_Disable APB4 Clock Enable Disable
  * @brief  Enable or disable the High Speed APB (APB4) peripheral clock.
  * @note   After reset, the peripheral clock (used for registers read/write access)
  *         is disabled and the application software has to enable this clock before
  *         using it.
  * @{
  */
#define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR4, RCC_APBENR4_SYSCFGEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR4, RCC_APBENR4_SYSCFGEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)
#define __HAL_RCC_VREFBUF_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR4, RCC_APBENR4_VREFBUFEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR4, RCC_APBENR4_VREFBUFEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)
#define __HAL_RCC_PWR_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR4, RCC_APBENR4_PWREN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR4, RCC_APBENR4_PWREN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)
#define __HAL_RCC_ADC1_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR4, RCC_APBENR4_ADC1EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR4, RCC_APBENR4_ADC1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)
#define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR4, RCC_APBENR4_ADC2EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR4, RCC_APBENR4_ADC2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)
#define __HAL_RCC_DAC_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR4, RCC_APBENR4_DACEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR4, RCC_APBENR4_DACEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)
#define __HAL_RCC_OPA_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR4, RCC_APBENR4_OPAEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR4, RCC_APBENR4_OPAEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)
#define __HAL_RCC_COMP_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APBENR4, RCC_APBENR4_COMPEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APBENR4, RCC_APBENR4_COMPEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)
#define __HAL_RCC_SYSCFG_CLK_DISABLE()      (RCC->APBENR4 &= ~(RCC_APBENR4_SYSCFGEN))
#define __HAL_RCC_VREFBUF_CLK_DISABLE()     (RCC->APBENR4 &= ~(RCC_APBENR4_VREFBUFEN))
#define __HAL_RCC_PWR_CLK_DISABLE()         (RCC->APBENR4 &= ~(RCC_APBENR4_PWREN))
#define __HAL_RCC_ADC1_CLK_DISABLE()        (RCC->APBENR4 &= ~(RCC_APBENR4_ADC1EN))
#define __HAL_RCC_ADC2_CLK_DISABLE()        (RCC->APBENR4 &= ~(RCC_APBENR4_ADC2EN))
#define __HAL_RCC_DAC_CLK_DISABLE()         (RCC->APBENR4 &= ~(RCC_APBENR4_DACEN))
#define __HAL_RCC_OPA_CLK_DISABLE()         (RCC->APBENR4 &= ~(RCC_APBENR4_OPAEN))
#define __HAL_RCC_COMP_CLK_DISABLE()        (RCC->APBENR4 &= ~(RCC_APBENR4_COMPEN))
/**
  * @}
  */
/** @defgroup RCC_APB4_Peripheral_Clock_Enable_Disable_Status APB4 Peripheral Clock Enable Disable Status
  * @brief  Get the enable or disable status of the APB4 peripheral clock.
  * @note   After reset, the peripheral clock (used for registers read/write access)
  *         is disabled and the application software has to enable this clock before
  *         using it.
  * @{
  */
#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()      ((RCC->APBENR4 & (RCC_APBENR4_SYSCFGEN)) != RESET)
#define __HAL_RCC_VREFBUF_IS_CLK_ENABLED()     ((RCC->APBENR4 & (RCC_APBENR4_VREFBUFEN)) != RESET)
#define __HAL_RCC_PWR_IS_CLK_ENABLED()         ((RCC->APBENR4 & (RCC_APBENR4_PWREN)) != RESET)
#define __HAL_RCC_ADC1_IS_CLK_ENABLED()        ((RCC->APBENR4 & (RCC_APBENR4_ADC1EN)) != RESET)
#define __HAL_RCC_ADC2_IS_CLK_ENABLED()        ((RCC->APBENR4 & (RCC_APBENR4_ADC2EN)) != RESET)
#define __HAL_RCC_DAC_IS_CLK_ENABLED()         ((RCC->APBENR4 & (RCC_APBENR4_DACEN)) != RESET)
#define __HAL_RCC_OPA_IS_CLK_ENABLED()         ((RCC->APBENR4 & (RCC_APBENR4_OPAEN)) != RESET)
#define __HAL_RCC_COMP_IS_CLK_ENABLED()        ((RCC->APBENR4 & (RCC_APBENR4_COMPEN)) != RESET)

#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()     ((RCC->APBENR4 & (RCC_APBENR4_SYSCFGEN)) == RESET)
#define __HAL_RCC_VREFBUF_IS_CLK_DISABLED()    ((RCC->APBENR4 & (RCC_APBENR4_VREFBUFEN)) == RESET)
#define __HAL_RCC_PWR_IS_CLK_DISABLED()        ((RCC->APBENR4 & (RCC_APBENR4_PWREN)) == RESET)
#define __HAL_RCC_ADC1_IS_CLK_DISABLED()       ((RCC->APBENR4 & (RCC_APBENR4_ADC1EN)) == RESET)
#define __HAL_RCC_ADC2_IS_CLK_DISABLED()       ((RCC->APBENR4 & (RCC_APBENR4_ADC2EN)) == RESET)
#define __HAL_RCC_DAC_IS_CLK_DISABLED()        ((RCC->APBENR4 & (RCC_APBENR4_DACEN)) == RESET)
#define __HAL_RCC_OPA_IS_CLK_DISABLED()        ((RCC->APBENR4 & (RCC_APBENR4_OPAEN)) == RESET)
#define __HAL_RCC_COMP_IS_CLK_DISABLED()       ((RCC->APBENR4 & (RCC_APBENR4_COMPEN)) == RESET)
/**
  * @}
  */
/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
  * @brief  Force or release APB1 peripheral reset.
  * @{
  */
#define __HAL_RCC_APB1_FORCE_RESET()         (RCC->APBRSTR1 = 0xFFFFFFFFU)
#define __HAL_RCC_TIM1_FORCE_RESET()         (RCC->APBRSTR1 |= (RCC_APBRSTR1_TIM1RST))
#define __HAL_RCC_TIM2_FORCE_RESET()         (RCC->APBRSTR1 |= (RCC_APBRSTR1_TIM2RST))
#define __HAL_RCC_TIM3_FORCE_RESET()         (RCC->APBRSTR1 |= (RCC_APBRSTR1_TIM3RST))
#define __HAL_RCC_TIM6_FORCE_RESET()         (RCC->APBRSTR1 |= (RCC_APBRSTR1_TIM6RST))
#define __HAL_RCC_TIM7_FORCE_RESET()         (RCC->APBRSTR1 |= (RCC_APBRSTR1_TIM7RST))
#define __HAL_RCC_TIM8_FORCE_RESET()         (RCC->APBRSTR1 |= (RCC_APBRSTR1_TIM8RST))

#define __HAL_RCC_APB1_RELEASE_RESET()       (RCC->APBRSTR1 = 0x00)
#define __HAL_RCC_TIM1_RELEASE_RESET()       (RCC->APBRSTR1 &= ~(RCC_APBRSTR1_TIM1RST))
#define __HAL_RCC_TIM2_RELEASE_RESET()       (RCC->APBRSTR1 &= ~(RCC_APBRSTR1_TIM2RST))
#define __HAL_RCC_TIM3_RELEASE_RESET()       (RCC->APBRSTR1 &= ~(RCC_APBRSTR1_TIM3RST))
#define __HAL_RCC_TIM6_RELEASE_RESET()       (RCC->APBRSTR1 &= ~(RCC_APBRSTR1_TIM6RST))
#define __HAL_RCC_TIM7_RELEASE_RESET()       (RCC->APBRSTR1 &= ~(RCC_APBRSTR1_TIM7RST))
#define __HAL_RCC_TIM8_RELEASE_RESET()       (RCC->APBRSTR1 &= ~(RCC_APBRSTR1_TIM8RST))
/**
  * @}
  */

/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
  * @brief  Force or release APB2 peripheral reset.
  * @{
  */
#define __HAL_RCC_APB2_FORCE_RESET()         (RCC->APBRSTR2 = 0xFFFFFFFFU)
#define __HAL_RCC_EPWM_FORCE_RESET()        (RCC->APBRSTR2 |= (RCC_APBRSTR2_EPWMRST))
#define __HAL_RCC_LPTIM_FORCE_RESET()        (RCC->APBRSTR2 |= (RCC_APBRSTR2_LPTIMRST))

#define __HAL_RCC_APB2_RELEASE_RESET()       (RCC->APBRSTR2 = 0x00)
#define __HAL_RCC_EPWM_RELEASE_RESET()      (RCC->APBRSTR2 &= ~(RCC_APBRSTR2_EPWMRST))
#define __HAL_RCC_LPTIM_RELEASE_RESET()      (RCC->APBRSTR2 &= ~(RCC_APBRSTR2_LPTIMRST))
/**
  * @}
  */

/** @defgroup RCC_APB3_Force_Release_Reset APB3 Force Release Reset
  * @brief  Force or release APB3 peripheral reset.
  * @{
  */
#define __HAL_RCC_APB3_FORCE_RESET()         (RCC->APBRSTR3 = 0xFFFFFFFFU)
#define __HAL_RCC_UART1_FORCE_RESET()        (RCC->APBRSTR3 |= (RCC_APBRSTR3_UART1RST))
#define __HAL_RCC_UART2_FORCE_RESET()        (RCC->APBRSTR3 |= (RCC_APBRSTR3_UART2RST))
#define __HAL_RCC_USART_FORCE_RESET()        (RCC->APBRSTR3 |= (RCC_APBRSTR3_USARTRST))
#define __HAL_RCC_LPUART_FORCE_RESET()       (RCC->APBRSTR3 |= (RCC_APBRSTR3_LPUARTRST))
#define __HAL_RCC_I2C1_FORCE_RESET()         (RCC->APBRSTR3 |= (RCC_APBRSTR3_I2C1RST))
#define __HAL_RCC_I2C2_FORCE_RESET()         (RCC->APBRSTR3 |= (RCC_APBRSTR3_I2C2RST))
#define __HAL_RCC_SPI1_FORCE_RESET()         (RCC->APBRSTR3 |= (RCC_APBRSTR3_SPI1RST))
#define __HAL_RCC_SPI2_FORCE_RESET()         (RCC->APBRSTR3 |= (RCC_APBRSTR3_SPI2RST))
#define __HAL_RCC_FDCAN_FORCE_RESET()          (RCC->APBRSTR3 |= (RCC_APBRSTR3_FDCANRST))

#define __HAL_RCC_APB3_RELEASE_RESET()       (RCC->APBRSTR3 = 0x00)
#define __HAL_RCC_UART1_RELEASE_RESET()      (RCC->APBRSTR3 &= ~(RCC_APBRSTR3_UART1RST))
#define __HAL_RCC_UART2_RELEASE_RESET()      (RCC->APBRSTR3 &= ~(RCC_APBRSTR3_UART2RST))
#define __HAL_RCC_USART_RELEASE_RESET()      (RCC->APBRSTR3 &= ~(RCC_APBRSTR3_USARTRST))
#define __HAL_RCC_LPUART_RELEASE_RESET()     (RCC->APBRSTR3 &= ~(RCC_APBRSTR3_LPUARTRST))
#define __HAL_RCC_I2C1_RELEASE_RESET()       (RCC->APBRSTR3 &= ~(RCC_APBRSTR3_I2C1RST))
#define __HAL_RCC_I2C2_RELEASE_RESET()       (RCC->APBRSTR3 &= ~(RCC_APBRSTR3_I2C2RST))
#define __HAL_RCC_SPI1_RELEASE_RESET()       (RCC->APBRSTR3 &= ~(RCC_APBRSTR3_SPI1RST))
#define __HAL_RCC_SPI2_RELEASE_RESET()       (RCC->APBRSTR3 &= ~(RCC_APBRSTR3_SPI2RST))
#define __HAL_RCC_FDCAN_RELEASE_RESET()        (RCC->APBRSTR3 &= ~(RCC_APBRSTR3_FDCANRST))
/**
  * @}
  */

/** @defgroup RCC_APB4_Force_Release_Reset APB4 Force Release Reset
  * @brief  Force or release APB4 peripheral reset.
  * @{
  */
#define __HAL_RCC_APB4_FORCE_RESET()         (RCC->APBRSTR4 = 0xFFFFFFFFU)
#define __HAL_RCC_SYSCFG_FORCE_RESET()       (RCC->APBRSTR4 |= (RCC_APBRSTR4_SYSCFGRST))
#define __HAL_RCC_VREFBUF_FORCE_RESET()      (RCC->APBRSTR4 |= (RCC_APBRSTR4_VREFBUFRST))
#define __HAL_RCC_PWR_FORCE_RESET()          (RCC->APBRSTR4 |= (RCC_APBRSTR4_PWRRST))
#define __HAL_RCC_ADC1_FORCE_RESET()         (RCC->APBRSTR4 |= (RCC_APBRSTR4_ADC1RST))
#define __HAL_RCC_ADC2_FORCE_RESET()         (RCC->APBRSTR4 |= (RCC_APBRSTR4_ADC2RST))
#define __HAL_RCC_DAC_FORCE_RESET()          (RCC->APBRSTR4 |= (RCC_APBRSTR4_DACRST))
#define __HAL_RCC_OPA_FORCE_RESET()          (RCC->APBRSTR4 |= (RCC_APBRSTR4_OPARST))
#define __HAL_RCC_COMP_FORCE_RESET()         (RCC->APBRSTR4 |= (RCC_APBRSTR4_COMPRST))

#define __HAL_RCC_APB4_RELEASE_RESET()       (RCC->APBRSTR4 = 0x00)
#define __HAL_RCC_SYSCFG_RELEASE_RESET()     (RCC->APBRSTR4 &= ~(RCC_APBRSTR4_SYSCFGRST))
#define __HAL_RCC_VREFBUF_RELEASE_RESET()    (RCC->APBRSTR4 &= ~(RCC_APBRSTR4_VREFBUFRST))
#define __HAL_RCC_PWR_RELEASE_RESET()        (RCC->APBRSTR4 &= ~(RCC_APBRSTR4_PWRRST))
#define __HAL_RCC_ADC1_RELEASE_RESET()       (RCC->APBRSTR4 &= ~(RCC_APBRSTR4_ADC1RST))
#define __HAL_RCC_ADC2_RELEASE_RESET()       (RCC->APBRSTR4 &= ~(RCC_APBRSTR4_ADC2RST))
#define __HAL_RCC_DAC_RELEASE_RESET()        (RCC->APBRSTR4 &= ~(RCC_APBRSTR4_DACRST))
#define __HAL_RCC_OPA_RELEASE_RESET()        (RCC->APBRSTR4 &= ~(RCC_APBRSTR4_OPARST))
#define __HAL_RCC_COMP_RELEASE_RESET()       (RCC->APBRSTR4 &= ~(RCC_APBRSTR4_COMPRST))
/**
  * @}
  */

/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
  * @brief  Force or release AHB1 peripheral reset.
  * @{
  */
#define __HAL_RCC_AHB1_FORCE_RESET()         (RCC->AHBRSTR1 = 0xFFFFFFFFU)
#define __HAL_RCC_DMA_FORCE_RESET()          (RCC->AHBRSTR1 |= (RCC_AHBRSTR1_DMARST))
#define __HAL_RCC_CRC_FORCE_RESET()          (RCC->AHBRSTR1 |= (RCC_AHBRSTR1_CRCRST))

#define __HAL_RCC_AHB1_RELEASE_RESET()       (RCC->AHBRSTR1 = 0x00)
#define __HAL_RCC_DMA_RELEASE_RESET()        (RCC->AHBRSTR1 &= ~(RCC_AHBRSTR1_DMARST))
#define __HAL_RCC_CRC_RELEASE_RESET()        (RCC->AHBRSTR1 &= ~(RCC_AHBRSTR1_CRCRST))
/**
  * @}
  */

/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Force Release Reset
  * @brief  Force or release APB2 peripheral reset.
  * @{
  */
#define __HAL_RCC_AHB2_FORCE_RESET()        (RCC->AHBRSTR2 = 0xFFFFFFFFU)
#define __HAL_RCC_GPIOA_FORCE_RESET()       (RCC->AHBRSTR2 |= (RCC_AHBRSTR2_GPIOARST))
#define __HAL_RCC_GPIOB_FORCE_RESET()       (RCC->AHBRSTR2 |= (RCC_AHBRSTR2_GPIOBRST))
#define __HAL_RCC_GPIOC_FORCE_RESET()       (RCC->AHBRSTR2 |= (RCC_AHBRSTR2_GPIOCRST))
#define __HAL_RCC_GPIOD_FORCE_RESET()       (RCC->AHBRSTR2 |= (RCC_AHBRSTR2_GPIODRST))

#define __HAL_RCC_AHB2_RELEASE_RESET()      (RCC->AHBRSTR2 = 0x00)
#define __HAL_RCC_GPIOA_RELEASE_RESET()     (RCC->AHBRSTR2 &= ~(RCC_AHBRSTR2_GPIOARST))
#define __HAL_RCC_GPIOB_RELEASE_RESET()     (RCC->AHBRSTR2 &= ~(RCC_AHBRSTR2_GPIOBRST))
#define __HAL_RCC_GPIOC_RELEASE_RESET()     (RCC->AHBRSTR2 &= ~(RCC_AHBRSTR2_GPIOCRST))
#define __HAL_RCC_GPIOD_RELEASE_RESET()     (RCC->AHBRSTR2 &= ~(RCC_AHBRSTR2_GPIODRST))
/**
  * @}
  */

/** @defgroup RCC_HSI_Configuration HSI Configuration
  * @{
  */

/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
  * @note   HSI can not be stopped if it is used as system clock source. In this case,
  *         you have to select another source of the system clock then stop the HSI.
  * @note   After enabling the HSI, the application software should wait on HSIRDY
  *         flag to be set indicating that HSI clock is stable and can be used as
  *         system clock source.
  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
  *         clock cycles.
  */
#define __HAL_RCC_HSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSION)
#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)

/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
  * @note   The calibration is used to compensate for the variations in voltage
  *         and temperature that influence the frequency of the internal HSI RC.
  * @param  __HSICALIBRATIONVALUE__ specifies the calibration trimming value
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_HSICALIBRATION_8MHz
  *            @arg @ref RCC_HSICALIBRATION_16MHz
  *            @arg @ref RCC_HSICALIBRATION_24MHz
  *            @arg @ref RCC_HSICALIBRATION_48MHz
  * @retval None
  */
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
                                 MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_HSI_FS | RCC_ICSCR_HSI_TRIMCR), (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSI_TRIMCR_Pos)

/** @brief  Macro to configure the HSISYS clock.
  * @param  __HSIDIV__ specifies the HSI division factor.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_HSI_DIV1   HSI clock source is divided by 1
  *            @arg @ref RCC_HSI_DIV2   HSI clock source is divided by 2
  *            @arg @ref RCC_HSI_DIV4   HSI clock source is divided by 4
  *            @arg @ref RCC_HSI_DIV8   HSI clock source is divided by 8
  */
#define __HAL_RCC_HSI_CONFIG(__HSIDIV__) \
                 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, (__HSIDIV__))

/**
  * @brief    Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
  *           in STOP mode to be quickly available as kernel clock for I2Cs.
  * @note     Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
  *           speed because of the HSI startup time.
  * @note     The enable of this function has not effect on the HSION bit.
  * @retval None
  */
#define __HAL_RCC_HSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_HSIKERON)

#define __HAL_RCC_HSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
/**
  * @}
  */

/** @defgroup RCC_LSI_Configuration  LSI Configuration
  * @{
  */

/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
  * @note   After enabling the LSI, the application software should wait on
  *         LSIRDY flag to be set indicating that LSI clock is stable and can
  *         be used to clock the IWDG and/or the RTC.
  */
#define __HAL_RCC_LSI_ENABLE()  SET_BIT(RCC->BDCR, RCC_BDCR_LSION)

/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
  * @note   LSI can not be disabled if the IWDG is running.
  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
  *         clock cycles.
  */
#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSION)

/**
  * @}
  */

/** @defgroup RCC_HSE_Configuration HSE Configuration
  * @{
  */

/**
  * @brief  Macro to configure the External High Speed oscillator (HSE).
  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
  *         supported by this macro. User should request a transition to HSE Off
  *         first and then HSE On or HSE Bypass.
  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
  *         software should wait on HSERDY flag to be set indicating that HSE clock
  *         is stable and can be used to clock the PLL and/or system clock.
  * @note   HSE state can not be changed if it is used directly or through the
  *         PLL as system clock. In this case, you have to select another source
  *         of the system clock then change the HSE state (ex. disable it).
  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
  * @note   This function reset the CSSON bit, so if the clock security system(CSS)
  *         was previously enabled you have to enable it again after calling this
  *         function.
  * @param  __STATE__ specifies the new state of the HSE.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
  *                              6 HSE oscillator clock cycles.
  *            @arg @ref RCC_HSE_ON turn ON the HSE oscillator
  *            @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
  */
#define __HAL_RCC_HSE_CONFIG(__STATE__)                                     \
                    do{                                                     \
                      if ((__STATE__) == RCC_HSE_ON)                        \
                      {                                                     \
                        SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
                      }                                                     \
                      else if ((__STATE__) == RCC_HSE_OFF)                  \
                      {                                                     \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
                      }                                                     \
                      else if ((__STATE__) == RCC_HSE_BYPASS)               \
                      {                                                     \
                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);                    \
                        SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
                      }                                                     \
                      else                                                  \
                      {                                                     \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
                      }                                                     \
                    }while(0U)

/**
  * @brief  Macro to configure the HSE frequency range.
  * @param  __FREQ__ specifies the HSE frequency range.
  *          This parameter can be one of the following values:
  *              @arg @ref RCC_HSE_4_8MHz  
  *              @arg @ref RCC_HSE_8_16MHz 
  *              @arg @ref RCC_HSE_16_24MHz
  *              @arg @ref RCC_HSE_24_32MHz
  */
#define __HAL_RCC_HSE_FREQ_CONFIG(__FREQ__)    MODIFY_REG(RCC->ECSCR, RCC_ECSCR_HSE_DRV, (__FREQ__))

/**
  * @brief    Macros to enable the analog filtering of the External High Speed oscillator (HSE).
  * @retval None
  */
#define __HAL_RCC_HSE_FILTER_ENABLE()     CLEAR_BIT(RCC->ECSCR, RCC_ECSCR_HSE_FILT_ENB)

/**
  * @brief    Macros to disable the analog filtering of the External High Speed oscillator (HSE).
  * @retval None
  */
#define __HAL_RCC_HSE_FILTER_DISABLE()    SET_BIT(RCC->ECSCR, RCC_ECSCR_HSE_FILT_ENB)

/** @brief  Macro to configure the HSE settling time.
  * @param  __TIME__ specifies the HSE settling time.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_HSE_STARTUP_NONE     Direct output regardless of stabilization time.
  *            @arg @ref RCC_HSE_STARTUP_LOW      It is output after 2048 HSE clock cycles. 
                                                  If HSEBYP is set, it is output after 1024 clock cycles.
  *            @arg @ref RCC_HSE_STARTUP_MEDIUM   It is output after 4096 HSE clock cycles.
                                                  If HSEBYP is set, it is output after 2048 clock cycles.
  *            @arg @ref RCC_HSE_STARTUP_HIGH     It is output after 8192 HSE clock cycles.
                                                  If HSEBYP is set, it is output after 4096 clock cycles.
  */
#define __HAL_RCC_HSE_STARTUP_DELAY(__TIME__)   MODIFY_REG(RCC->ECSCR, RCC_ECSCR_HSE_RDYSEL ,(__TIME__))
/** 
  * @}
  */

/** @defgroup RCC_LSE_Configuration LSE Configuration
  * @{
  */

/**
  * @brief  Macro to configure the External Low Speed oscillator (LSE).
  * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
  * @note   As the LSE is in the Backup domain and write access is denied to
  *         this domain after reset, you have to enable write access using
  *         @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
  *         (to be done once after reset).
  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
  *         software should wait on LSERDY flag to be set indicating that LSE clock
  *         is stable and can be used to clock the RTC.
  * @param  __STATE__ specifies the new state of the LSE.
  *         This parameter can be one of the following values:
  *            @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
  *                              6 LSE oscillator clock cycles.
  *            @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
  *            @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
  */
#define __HAL_RCC_LSE_CONFIG(__STATE__)                                     \
                    do{                                                     \
                      if ((__STATE__) == RCC_LSE_ON)                        \
                      {                                                     \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                   \
                      }                                                     \
                      else if ((__STATE__) == RCC_LSE_OFF)                  \
                      {                                                     \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);                 \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                \
                      }                                                     \
                      else if ((__STATE__) == RCC_LSE_BYPASS)               \
                      {                                                     \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                  \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                   \
                      }                                                     \
                      else                                                  \
                      {                                                     \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);                 \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                \
                      }                                                     \
                    }while(0U)

/**
  * @brief  Macro to configure the LSE drive capability.
  * @param  __DRIVER__ specifies the LSE drive capability.
  *          This parameter can be one of the following values:
  *              @arg @ref RCC_LSEDRIVE_LOW
  *              @arg @ref RCC_LSEDRIVE_MEDIUM
  *              @arg @ref RCC_LSEDRIVE_HIGH
  *              @arg @ref RCC_LSEDRIVE_VERY_HIGH
  */
#define __HAL_RCC_LSE_DRIVER_CONFIG(__DRIVER__)   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__DRIVER__))

/** @brief  Macro to configure the LSE settling time.
  * @param  __TIME__ specifies the LSE settling time.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_LSE_STARTUP_NONE     Direct output regardless of stabilization time.
  *            @arg @ref RCC_LSE_STARTUP_LOW      It is output after 2048 LSE clock cycles. 
                                                  If LSEBYP is set, it is output after 1024 clock cycles.
  *            @arg @ref RCC_LSE_STARTUP_MEDIUM   It is output after 4096 LSE clock cycles.
                                                  If LSEBYP is set, it is output after 2048 clock cycles.
  *            @arg @ref RCC_LSE_STARTUP_HIGH     It is output after 8192 LSE clock cycles.
                                                  If LSEBYP is set, it is output after 4096 clock cycles.
  */
#define __HAL_RCC_LSE_STARTUP_DELAY(__TIME__)   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSE_RDYSEL ,(__TIME__))
/**
  * @}
  */

/** @defgroup RCC_PLL_Configuration PLL Configuration
  * @{
  */

/** @brief Macro to enable the main PLL.
  * @note   After enabling the main PLL, the application software should wait on
  *         PLLRDY flag to be set indicating that PLL clock is stable and can
  *         be used as system clock source.
  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
  */
#define __HAL_RCC_PLL_ENABLE()          SET_BIT(RCC->CR, RCC_CR_PLLON)

/** @brief Macro to disable the main PLL.
  * @note   The main PLL can not be disabled if it is used as system clock source
  */
#define __HAL_RCC_PLL_DISABLE()         CLEAR_BIT(RCC->CR, RCC_CR_PLLON)

/** @brief Macro to configure the main PLL clock source and multiplication factors.
  * @note   This function must be used only when the main PLL is disabled.
  *
  * @param  __RCC_PLLSOURCE__ specifies the PLL entry clock source.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
  *            @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
  * @param  __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
  *          This parameter can be one of the following values:
  *             @arg @ref RCC_PLL_MUL2    PLLVCO = PLL clock entry x 2
  *             @arg @ref RCC_PLL_MUL3    PLLVCO = PLL clock entry x 3
  *                       ......
  *             @arg @ref RCC_PLL_MUL15   PLLVCO = PLL clock entry x 15
  *             @arg @ref RCC_PLL_MUL16   PLLVCO = PLL clock entry x 15
  */
#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
          MODIFY_REG(RCC->PLLCFGR1, (RCC_PLLCFGR1_PLLSRC | RCC_PLLCFGR1_PLLMUL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))

/** @brief  Get oscillator clock selected as PLL input clock
  * @retval The clock source used for PLL entry. The returned value can be one
  *         of the following:
  *             @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL input clock
  *             @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL input clock
  */
#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->PLLCFGR1, RCC_PLLCFGR1_PLLSRC)))

/**
  * @}
  */

/** @defgroup RCC_Get_Clock_source Get Clock source
  * @{
  */

/**
  * @brief  Macro to configure the system clock source.
  * @param  __SYSCLKSOURCE__ specifies the system clock source.
  *          This parameter can be one of the following values:
  *              @arg @ref RCC_SYSCLKSOURCE_HSISYS HSISYS oscillator is used as system clock source.
  *              @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
  *              @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
  */
#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
                  MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, (__SYSCLKSOURCE__))

/** @brief  Macro to get the clock source used as system clock.
  * @retval The clock source used as system clock. The returned value can be one
  *         of the following:
  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSISYS HSISYS used as system clock
  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE    HSE used as system clock
  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
  */
#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS)))

/**
  * @}
  */

/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
  * @{
  */

/** @brief  Macro to configure the MCO1 clock.
  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
  *         This parameter can be one of the following values:
  *            @arg @ref RCC_MCOSOURCE_NOCLOCK  MCO output disabled, no clock on MCO
  *            @arg @ref RCC_MCOSOURCE_SYSCLK   system  clock selected as MCO source
  *            @arg @ref RCC_MCOSOURCE_HSI      HSI clock selected as MCO source
  *            @arg @ref RCC_MCOSOURCE_HSE      HSE clock selected as MCO sourcee
  *            @arg @ref RCC_MCOSOURCE_PLLCLK   main PLL clock selected as MCO source
  *            @arg @ref RCC_MCOSOURCE_LSI      LSI clock selected as MCO source
  *            @arg @ref RCC_MCOSOURCE_LSE      LSE clock selected as MCO source
  *            @arg @ref RCC_MCOSOURCE_HSI10M   HSI10M clock selected as MCO source
  *            @arg @ref RCC_MCOSOURCE_HCLK     HCLK clock selected as MCO source
  *            @arg @ref RCC_MCOSOURCE_PCLK1    APB1 clock selected as MCO sourcee
  *            @arg @ref RCC_MCOSOURCE_PCLK2    APB2 clock selected as MCO source
  * @param  __MCODIV__ specifies the MCO clock prescaler.
  *         This parameter can be one of the following values:
  *            @arg @ref RCC_MCODIV_1    no division applied to MCO clock
  *            @arg @ref RCC_MCODIV_2    division by 2 applied to MCO clock
  *            @arg @ref RCC_MCODIV_4    division by 4 applied to MCO clock
  *            @arg @ref RCC_MCODIV_8    division by 8 applied to MCO clock
  *            @arg @ref RCC_MCODIV_16   division by 16 applied to MCO clock
  *            @arg @ref RCC_MCODIV_32   division by 32 applied to MCO clock
  *            @arg @ref RCC_MCODIV_64   division by 64 applied to MCO clock
  *            @arg @ref RCC_MCODIV_128  division by 128 applied to MCO clock
  *            @arg @ref RCC_MCODIV_256  division by 256 applied to MCO clock
  */

#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__)   \
                   MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCO1SEL | RCC_CFGR1_MCO1PRE), (__MCOCLKSOURCE__) | (__MCODIV__))

/** @brief  Macro to configure the MCO2 clock.
  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
  *         This parameter can be one of the following values:
  *            @arg @ref RCC_MCOSOURCE_NOCLOCK  MCO output disabled, no clock on MCO
  *            @arg @ref RCC_MCOSOURCE_SYSCLK   system  clock selected as MCO source
  *            @arg @ref RCC_MCOSOURCE_HSI      HSI clock selected as MCO source
  *            @arg @ref RCC_MCOSOURCE_HSE      HSE clock selected as MCO sourcee
  *            @arg @ref RCC_MCOSOURCE_PLLCLK   main PLL clock selected as MCO source
  *            @arg @ref RCC_MCOSOURCE_LSI      LSI clock selected as MCO source
  *            @arg @ref RCC_MCOSOURCE_LSE      LSE clock selected as MCO source
  *            @arg @ref RCC_MCOSOURCE_HSI10M   HSI10M clock selected as MCO source
  *            @arg @ref RCC_MCOSOURCE_HCLK     HCLK clock selected as MCO source
  *            @arg @ref RCC_MCOSOURCE_PCLK1    APB1 clock selected as MCO sourcee
  *            @arg @ref RCC_MCOSOURCE_PCLK2    APB2 clock selected as MCO source
  * @param  __MCODIV__ specifies the MCO clock prescaler.
  *         This parameter can be one of the following values:
  *            @arg @ref RCC_MCODIV_1    no division applied to MCO clock
  *            @arg @ref RCC_MCODIV_2    division by 2 applied to MCO clock
  *            @arg @ref RCC_MCODIV_4    division by 4 applied to MCO clock
  *            @arg @ref RCC_MCODIV_8    division by 8 applied to MCO clock
  *            @arg @ref RCC_MCODIV_16   division by 16 applied to MCO clock
  *            @arg @ref RCC_MCODIV_32   division by 32 applied to MCO clock
  *            @arg @ref RCC_MCODIV_64   division by 64 applied to MCO clock
  *            @arg @ref RCC_MCODIV_128  division by 128 applied to MCO clock
  *            @arg @ref RCC_MCODIV_256  division by 256 applied to MCO clock
  */

#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__)   \
                   MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCO2SEL | RCC_CFGR1_MCO2PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)) << 8U)
/**
  * @}
  */

/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
* @{
*/

/** @brief Macro to configure the RTC clock (RTCCLK).
  * @note   As the RTC clock configuration bits are in the Backup domain and write
  *         access is denied to this domain after reset, you have to enable write
  *         access using the Power Backup Access macro before to configure
  *         the RTC clock source (to be done once after reset).
  * @note   Once the RTC clock is configured it can't be changed unless the
  *         Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
  *         a Power On Reset (POR).
  *
  * @param  __RTC_CLKSOURCE__ specifies the RTC clock source.
  *          This parameter can be one of the following values:
  *             @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock
  *             @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
  *             @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE divided by 32 selected as RTC clock
  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as RTC clock
  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
  *         work in STOP and STANDBY modes, and can be used as wakeup source.
  *         However, when the HSE clock is used as RTC clock source, the RTC
  *         cannot be used in STOP and STANDBY modes.
  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
  *         RTC clock source).
  */
#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
                                                do { \
                                                  MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, ((__RTC_CLKSOURCE__) & RCC_BDCR_RTCSEL)); \
                                                  if (((__RTC_CLKSOURCE__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL){ \
                                                      MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_RTC_HSEDIV_SEL, ((__RTC_CLKSOURCE__) & RCC_CCIPR2_RTC_HSEDIV_SEL)); \
                                                    } else { \
                                                      CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_RTC_HSEDIV_SEL); \
                                                    } \
                                                } while(0)
/** @brief Macro to get the RTC clock source.
  * @retval The clock source can be one of the following values:
  *            @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock
  *            @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
  *            @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE divided by 32 selected as RTC clock
  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as RTC clock
  */
#define __HAL_RCC_GET_RTC_SOURCE() (((RCC->BDCR & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
                                    ((RCC->CCIPR2 & RCC_CCIPR2_RTC_HSEDIV_SEL) | (RCC->BDCR & RCC_BDCR_RTCSEL)) : \
                                    (RCC->BDCR & RCC_BDCR_RTCSEL))

/** @brief Macro to enable the RTC clock.
  * @note   These macros must be used only after the RTC clock source was selected.
  */
#define __HAL_RCC_RTC_ENABLE()          SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)

/** @brief Macro to disable the RTC clock.
  * @note  These macros must be used only after the RTC clock source was selected.
  */
#define __HAL_RCC_RTC_DISABLE()         CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)

/** @brief  Macro to force the Backup domain reset.
  * @note   This function resets the RTC peripheral (including the backup registers)
  *         and the RTC clock source selection in RCC_BDCR register.
  */
#define __HAL_RCC_BACKUPRESET_FORCE()   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)

/** @brief  Macros to release the Backup domain reset.
  */
#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)

/**
  * @}
  */

/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
  * @brief macros to manage the specified RCC Flags and interrupts.
  * @{
  */

/** @brief Enable RCC interrupt.
  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
  *          This parameter can be any combination of the following values:
  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
  *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
  */
#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (RCC->CIER |= (__INTERRUPT__))

/** @brief Disable RCC interrupt.
  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
  *          This parameter can be any combination of the following values:
  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
  *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
  */
#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (RCC->CIER &= (~(__INTERRUPT__)))

/** @brief Clear the RCC's interrupt pending bits.
  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
  *          This parameter can be any combination of the following values:
  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
  *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
  *            @arg @ref RCC_IT_CSS Clock Security System interrupt
  */
#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))

/** @brief Check the RCC's interrupt has occurred or not.
  * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
  *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
  *            @arg @ref RCC_IT_CSS Clock Security System interrupt
  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
  */
#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))

/** @brief Set RMVF bit to clear the reset flags.
  *         The reset flags are RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PWRRST, RCC_FLAG_SFTRST,
  *         RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST, RCC_FLAG_EPWM_PRST, RCC_FLAG_EPWM_SFTRST,
  *         RCC_FLAG_PLLULRST
  */
#define __HAL_RCC_CLEAR_RESET_FLAGS()     do{ \
                                            SET_BIT(RCC->CSR, RCC_CSR_RMVF); \
                                            CLEAR_BIT(RCC->CSR, RCC_CSR_RMVF); \
                                          }while(0)

/** @brief  Check RCC flag is set or not.
  * @param  __FLAG__ specifies the flag to check.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
  *            @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
  *            @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
  *            @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
  *            @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
               @arg @ref RCC_FLAG_EPWM_PRST EPWM APB reset flag
               @arg @ref RCC_FLAG_EPWM_SFTRST EPWM software reset flag
               @arg @ref RCC_FLAG_PLLULRST PLL unlock reset flag
               @arg @ref RCC_FLAG_OBLRST Option byte loader reset flag
  *            @arg @ref RCC_FLAG_PINRST  Pin reset.
  *            @arg @ref RCC_FLAG_PWRRST  POR/PDR reset.
  *            @arg @ref RCC_FLAG_SFTRST  Software reset.
  *            @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
  *            @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
  *            @arg @ref RCC_FLAG_LPWRRST Low Power reset.
  * @retval The new state of __FLAG__ (TRUE or FALSE).
  */
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == CR_REG_INDEX)?   RCC->CR  : \
                                        ((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : RCC->CSR)) & \
                                       (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U)

/**
  * @}
  */

/**
  * @}
  */

/* Include RCC HAL Extension module */
#include "py32f420_hal_rcc_ex.h"

/* Exported functions --------------------------------------------------------*/
/** @addtogroup RCC_Exported_Functions
  * @{
  */

/** @addtogroup RCC_Exported_Functions_Group1
  * @{
  */

/* Initialization and de-initialization functions  ******************************/
HAL_StatusTypeDef HAL_RCC_DeInit(void);
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency);

/**
  * @}
  */

/** @addtogroup RCC_Exported_Functions_Group2
  * @{
  */

/* Peripheral Control functions  ************************************************/
void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
void              HAL_RCC_EnableCSS(void);
uint32_t          HAL_RCC_GetSysClockFreq(void);
uint32_t          HAL_RCC_GetHCLKFreq(void);
uint32_t          HAL_RCC_GetPCLK1Freq(void);
uint32_t          HAL_RCC_GetPCLK2Freq(void);
void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency);

/* CSS NMI IRQ handler */
void              HAL_RCC_NMI_IRQHandler(void);

/* User Callbacks in non blocking mode (IT mode) */
void              HAL_RCC_CSSCallback(void);

/**
  * @}
  */

/**
  * @}
  */

/** @addtogroup RCC_Private_Constants
  * @{
  */

/** @defgroup RCC_Timeout RCC Timeout
  * @{
  */
/* Disable Backup domain write protection state change timeout */
#define RCC_DBP_TIMEOUT_VALUE          100U    /* 100 ms */
/* LSE state change timeout */
#define RCC_LSE_TIMEOUT_VALUE          LSE_STARTUP_TIMEOUT
#define CLOCKSWITCH_TIMEOUT_VALUE      5000    /* 5 s    */
#define HSE_TIMEOUT_VALUE              HSE_STARTUP_TIMEOUT
#define HSI_TIMEOUT_VALUE              2U      /* 2 ms (minimum Tick + 1) */
#define HSI48M_TIMEOUT_VALUE           2U      /* 2 ms (minimum Tick + 1) */
#define LSI_TIMEOUT_VALUE              2U      /* 2 ms (minimum Tick + 1) */
#define PLL_TIMEOUT_VALUE              3U      /* 3 ms (minimum Tick + 1) */
#define AHB_25MHZ                     (25000000U)
#define AHB_50MHZ                     (50000000U)
#define AHB_75MHZ                     (75000000U)
#define AHB_100MHZ                    (100000000U)
#define AHB_125MHZ                    (125000000U)
#define AHB_150MHZ                    (150000000U)
#define AHB_175MHZ                    (175000000U)
/**
  * @}
  */

/* Defines used for Flags */
#define CR_REG_INDEX                     ((uint8_t)1)
#define BDCR_REG_INDEX                   ((uint8_t)2)
#define CSR_REG_INDEX                    ((uint8_t)3)

#define RCC_FLAG_MASK                    ((uint8_t)0x1F)

/**
  * @}
  */

/** @addtogroup RCC_Private_Macros
  * @{
  */

#define IS_RCC_PLLSOURCE(__SOURCE__)                  (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
                                                       ((__SOURCE__) == RCC_PLLSOURCE_HSE))

#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__)         (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \
                                                       (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
                                                       (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
                                                       (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
                                                       (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
                                               
#define IS_RCC_HSE(__HSE__)                           (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
                                                       ((__HSE__) == RCC_HSE_BYPASS))
                             
#define IS_RCC_LSE(__LSE__)                           (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
                                                       ((__LSE__) == RCC_LSE_BYPASS))
                             
#define IS_RCC_HSI(__HSI__)                           (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))

#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) (((__VALUE__) == RCC_HSICALIBRATION_8MHz)      || \
                                                 ((__VALUE__) == RCC_HSICALIBRATION_16MHz)     || \
                                                 ((__VALUE__) == RCC_HSICALIBRATION_24MHz)     || \
                                                 ((__VALUE__) == RCC_HSICALIBRATION_48MHz))

#define IS_RCC_HSIDIV(__DIV__)            (((__DIV__) == RCC_HSI_DIV1)  || ((__DIV__) == RCC_HSI_DIV2) || \
                                           ((__DIV__) == RCC_HSI_DIV4)  || ((__DIV__) == RCC_HSI_DIV8))

#define IS_RCC_CALIBRATION_VALUE(__VALUE__)           ((__VALUE__) <= 0x1FU)

#define IS_RCC_LSI(__LSI__)                           (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))

#define IS_RCC_PLL(__PLL__)                           (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
                                                       ((__PLL__) == RCC_PLL_ON))

#define IS_RCC_CLOCKTYPE(CLK)                         ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
                                                       (((CLK) & RCC_CLOCKTYPE_HCLK)   == RCC_CLOCKTYPE_HCLK)   || \
                                                       (((CLK) & RCC_CLOCKTYPE_PCLK1)  == RCC_CLOCKTYPE_PCLK1)  || \
                                                       (((CLK) & RCC_CLOCKTYPE_PCLK2)  == RCC_CLOCKTYPE_PCLK2))
                               
#define IS_RCC_SYSCLKSOURCE(__SOURCE__)               (((__SOURCE__) == RCC_SYSCLKSOURCE_HSISYS) || \
                                                       ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
                                                       ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
                                         
#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__)        (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSISYS) || \
                                                       ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
                                                       ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
                                                
#define IS_RCC_HCLK(__HCLK__)                         (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
                                                       ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
                                                       ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
                                                       ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
                                                       ((__HCLK__) == RCC_SYSCLK_DIV512))
                               
#define IS_RCC_PCLK(__PCLK__)                         (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
                                                       ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
                                                       ((__PCLK__) == RCC_HCLK_DIV16))
                               
#define IS_RCC_MCO(__MCO__)                           (((__MCO__) == RCC_MCO1_PC9)  || ((__MCO__) == RCC_MCO1_PC14) || \
                                                       ((__MCO__) == RCC_MCO1_PD1)  || ((__MCO__) == RCC_MCO1_PD5)  || \
                                                       ((__MCO__) == RCC_MCO2_PA4)  || ((__MCO__) == RCC_MCO2_PA8)  || \
                                                       ((__MCO__) == RCC_MCO2_PC15) || ((__MCO__) == RCC_MCO2_PD11))

#define IS_RCC_MCODIV(__DIV__)                        (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
                                                       ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
                                                       ((__DIV__) == RCC_MCODIV_16) || ((__DIV__) == RCC_MCODIV_32) || \
                                                       ((__DIV__) == RCC_MCODIV_64) || ((__DIV__) == RCC_MCODIV_128) || \
                                                       ((__DIV__) == RCC_MCODIV_256))

#define IS_RCC_RTCCLKSOURCE(__SOURCE__)               (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \
                                                       ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
                                                       ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
                                                       ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32) || \
                                                       ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128) || \
                                                       ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8))

#define IS_RCC_HSE_FREQ(__DRIVER__)                (((__DRIVER__) == RCC_HSE_4_8MHz)  || \
                                                    ((__DRIVER__) == RCC_HSE_8_16MHz) || \
                                                    ((__DRIVER__) == RCC_HSE_16_24MHz) || \
                                                    ((__DRIVER__) == RCC_HSE_24_32MHz))
                                                       
#define IS_RCC_LSE_DRIVER(__DRIVER__)                 (((__DRIVER__) == RCC_LSEDRIVE_LOW)    || \
                                                       ((__DRIVER__) == RCC_LSEDRIVE_MEDIUM) || \
                                                       ((__DRIVER__) == RCC_LSEDRIVE_HIGH)   || \
                                                       ((__DRIVER__) == RCC_LSEDRIVE_VERY_HIGH ))
/**
  * @}
  */

/**
  * @}
  */

/**
  * @}
  */

#ifdef __cplusplus
}
#endif

#endif /* __PY32F420_HAL_RCC_H */

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